Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

<p>The Internet of Things (IoT) applies the sensors and microcontrollers links them through internet. The eventual objective low-power devices for is to lesser overall system power extend battery life. For development energy efficient IoT devices, novel adiabatic techniques are proposed. By improving performance comparator, one can improvise whole performance. efficacy computing depends on arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using such as DC-DB PFAL (Direct current diode-based positive feedback logic) MPFAL (Modify which well-suited with an extensive range applications (e.g. inbuilt analog digital converter). analysis, results compared together along other non designs already reported in literature. a way decrease dissipation transistor count binary circuits it primary concerns. From results, found that logic shows improvement power-delay-product 69%, 94% 90% MPFAL, ECRL respectively.</p> <p> </p>